The present invention relates to a phase-locked oscillation circuit system for producing a clock whose frequency is an integral multiple of the frequency of a signal produced by dividing the frequency of an input clock.
A conventional phase-locked oscillation circuit system is made up of two phase-locked oscillation circuits and which are interconnected in two stages. The oscillation circuits each has a phase comparator, a loop filter, a voltage controlled oscillator (VCO), and two frequency dividers. In this kind of circuit system, the loop filter of the first stage is provided with an extremely great time constant. Hence, even when the clock being inputted to the circuitry via an input terminal is shut off, the output of the first stage does not sharply change and, therefore, prevents the clock being outputted via an output terminal from undergoing a noticeable change.
Another conventional phase-locked oscillation circuit system has a switch, a frequency division timing control circuit, a constant voltage source, and a clock shut-off detector in addition to a phase-locked oscillation circuit which is made up of a phase comparator, a loop filter, a VCO, and two frequency dividers. In such a configuration, when the clock shut-off detector detects the shut-off of the input clock, the switch is so controlled as to connect the input of the VCO to the constant voltage source. As a result, the clock frequency appearing on an output terminal is maintained constant. After the input clock has been recovered, the frequency division timing control circuit delivers the output of one of the frequency dividers to the other frequency divider only once to thereby coincide with each phase of the input signal to the phase comparator. At the same time, the switch is operated again to connect the input of the VCO to the loop filter, reestablishing lock rapidly.
The problem with the two-stage oscillation circuit scheme is that since the time constant of the loop filter is great, the interval between the time when the phase comparator is brought out of lock and the time when it regains lock is extremely long. The single-stage oscillation circuit scheme is not satisfactory for the following reason. Specifically, though the output clock frequency is fixed while the input clock is shut off, the output frequency is seldom the same before and after the shutoff. Then, the clock appearing on the output terminal fluctuates when the input clock is shut off and recovered.